- The 16-layer HBM3e chips are expected to be rolled out in 2025
- New chips offer improved AI learning and inference capabilities
- Users can expect lower latency, Sk hynix claims
SK hynix has announced plans to add four additional layers to its 12-HI HBM3e memory chips to increase capacity.
The move will see the company increase capacity from 36GB to 48GB, and the semiconductor giant expects to begin distributing sample products in early 2025.
The announcement could deliver significant performance improvements for organizations ramping up AI development. HBM3e chips traditionally have a maximum of twelve layers, but with the arrival of HBM4, users can achieve better performance.
Stacked and ready
Company CEO Kwak Noh-Jung announced the launch at the recent SK AI Summit in Seoul, noting that the upgrade will significantly improve AI learning performance and inference capabilities.
“We stacked 16 DRAM chips to achieve a capacity of 48 GB and applied advanced MR-MUF technology proven for mass production. In addition, we are developing hybrid bonding technology as a backup process,” he said.
Kwak has added initial internal testing showing that the 16-layer HBM3e can improve both AI learning and inference by 18% and 34% respectively compared to previous 12-layer HBM3e
“The 16-layer HBM3E is expected to be released in 2025,” Kwak revealed.
HBM4 offers over 10 Gbps per pin compared to the high-end maximum of 9.2 Gbps of its predecessor. All told, this will unlock bandwidth capabilities of up to 1.5 TBps, compared to HBM3e’s 1.2-plus TBps.
Additionally, manufacturers expect HBM4 to deliver lower latency as well.
Under the hood of the 16-Hi product
In terms of design, the 16-Hi product has been developed using Mass Reflow-Molded Underfill (MR-MUF) technology. This next-generation technology allows warp-free stacking of chips that are 40% thinner than conventional alternatives.
This also provides improved heat dissipation thanks to the use of new protective materials, the company said.
Likewise, hybrid bonding has also delivered marked improvements. This means chips are bonded directly together without the need to create a ‘bump’ between them during stacking, SK Hynix noted.
“This reduces the overall thickness of the chip, allowing for high stacking,” the company said in an announcement. “SK hynix is looking at both advanced MR-MUF and hybrid connection methods for 16-layer and higher HBM products.”