In 2019, the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences (CAS) launched the “XiangShan” project, aiming to create a high-performance open-source RISC-V processor. The result of this effort was the XiangShan processor core, which has received much attention on GitHubwith over 4,500 stars and 630 forks so far.
XiangShan has also received support from several companies, leading to the establishment of a group focused on further developing the processor and promoting the RISC-V ecosystem.
The Beijing Institute of Open Source Chip (BOSC), a non-profit organization, was established to promote the development of XiangShan, with a focus on regular updates and improvements to the processor’s design, performance, and energy efficiency. The goal is to make XiangShan a competitive, open-source processor that can serve a wide range of applications.
The Linux of processors
XiangShan has now made his appearance at Fries 2024a symposium on High Performance Chips held in Stanford, California, in late August, which attracted the attention of ServeTheHomenoting that it is “a high-performance CPU design, rather than the lower-performance designs we’ve seen from others.”
The project, described in one of the XiangShan slides as “The Linux of Processors,” lays out a two-tier CPU core roadmap that highlights two architectures: Kunminghu, focused on the Arm Neoverse N2 and designed for high performance in servers and data centers, and Nanhu, focused on the Arm Cortex A76, focusing on power and area efficiency for industrial control applications. You can see a comparison in this image:
The XiangShan Project plans to improve its microarchitecture through a dual development team approach, focusing on agile development to refine high-performance open source processors, with annually committed test chips for each architecture to meet the needs of both industry and academia.
If ZHPatrick Kennedy notes: “It’s cool to see that there are essentially two RISC-V projects coming out of China that are directly targeting the performance and product segments of two Arm CPUs. We often see custom RISC-V designs, but these are more general-purpose chips.”