Samsung has used advanced computing models to accelerate the development of Selector-Only Memory (SOM), a new memory technology that combines non-volatility with DRAM-like read/write speeds and stackability.
Building on the company’s previous research in this area, SOM is based on cross-point memory architectures, similar to phase change memory and resistive RAM (RRAM), using stacked arrays of electrodes. Typically, these architectures require a selector transistor or diode to address specific memory cells and prevent unintended electrical paths.
Samsung has taken a new approach by exploring chalcogenide-based materials that function as both selectors and memory elements, introducing a new form of non-volatile memory.
A broader search
eeNews analogue reports that Samsung researchers will present their findings at this year’s International Electron Devices Meeting (IEDM), which takes place from December 7 to 11 in San Francisco. The South Korean tech giant will discuss how it has screened an extensive range of chalcogenide materials for SOM applications.
Samsung says its research examined more than 4,000 material combinations and narrowed them down to 18 promising candidates using Ab-initio-based computer modeling (see the diagram at the top of the page). The focus was on improving threshold voltage drift and optimizing the memory window – two key factors in SOM performance.
Traditional SOM research has been limited to the use of Ge, As, and Se chalcogenide systems found in ovonic threshold switches (OTS). However, Samsung says the extensive modeling process allowed for a broader search that took into account connection properties, thermal stability and device reliability to improve performance and efficiency.
In a follow-up IEDM presentation, eeNews analogue In their reports, IMEC researchers will discuss potential atomic mechanisms, such as local atomic bond rearrangement and atomic segregation, that could explain how the selector component in SOM works, further affecting the threshold voltage – an important factor in memory performance.