Huawei looks ready to launch a new server chip with HBM technology to challenge Xeon and Epyc; yes, that’s the same memory that powers AI GPUs from Nvidia and AMD
- Huawei may add HBM support to Kunpeng SoC
- There are indications that there is a replacement for the Kunpeng 920, launched in 2019
- New SoC with HBM can target HPC, rivals in the server market
Huawei engineers did that reportedly has released new Linux patches to enable driver support for High Bandwidth Memory (HBM) management on the company’s ARM-based Kunpeng high-performance SoC.
Debuting in January 2019 as the company’s first server CPU, the Kunpeng 920 is a 7nm processor with up to 64 cores based on the Armv8.2 architecture. It supports eight DDR4 memory channels and has a thermal design power (TDP) of up to 180W. While these specifications were competitive when they were first introduced, things have improved significantly since then.
The introduction of a new Kunpeng SoC with integrated HBM would align with industry trends as enterprises look to increase memory bandwidth and performance in response to increasingly demanding workloads. It could also signal Huawei’s efforts to maintain competitiveness in the HPC and server markets dominated by Intel Xeon and AMD EPYC.
No official announcement yet
PhoronixMichael Larabel notes that Huawei has not yet formally announced a new Kunpeng SoC (with or without HBM), and references to it are scarce. However, kernel patches have previously indicated that work is underway to integrate HBM into the platform.
The latest patches specifically address power control for HBM devices on the Kunpeng SoC, introducing the ability to enable or disable HBM caches depending on workload requirements.
The patch series contains detailed descriptions of this functionality. Huawei explains that HBM offers higher bandwidth, but consumes more power. The proposed drivers allow users to manage HBM’s energy consumption, optimizing energy consumption for workloads that do not require high memory bandwidth.
The patches also introduce a driver for HBM cache, allowing control of this feature in user space. By using HBM as a cache, operating systems can take advantage of the bandwidth benefits without having to be directly aware of the cache’s presence. When the workload is less demanding, the cache can be disabled to save energy.
While we don’t have any concrete details on future Kunpeng SoCs, HBM’s integration could allow them to compete more effectively against other ARM-based server processors, as well as Intel’s latest Xeon and AMD EPYC offerings.