Crucial technology critical to AI in hyperscalers gets a major update to improve performance, enhance functionality and extend security
- CXL 3.2 offers a series of important improvements
- Security updates are a major focus for 3.2
- CXL has become increasingly important in the age of AI
CXL Consortium has announced the release of its new Compute Express Link (CXL) 3.2 specifications, which add a range of optimized features to the technology.
In his announcementthe consortium revealed that the upgraded specification will enhance the monitoring and management capabilities of CXL Memory Device and enhance the functionality of CXL Memory Devices for both operating systems and applications.
Security improvements are also a major talking point with the introduction of the Trusted Security Protocol (TSP).
What can you expect from CXL 3.2
CXL plays a critical role in how GPUs and CPUs handle memory, standardizing communication between devices and reducing latency. All together, this helps make systems faster and more efficient when processing large amounts of data.
With the advent of generative AI, CXL has become increasingly important given the fast data processing requirements of applications, and this latest update will further enhance previous specifications, especially in the areas of monitoring and management of CXL memory devices.
The new specification includes a new CXL hot page monitoring unit (CHMU) specifically aimed at streamlining memory tiering.
Similarly, the consortium unveiled compatibility with PCIe Management Message Pass Through (MMPT) in addition to improvements to the online CXL firmware.
Security improvements are a key focus in this latest update through TSP, the consortium noted, including new meta-bit storage features, the extension of IDE protection, and improved compliance testing for interoperability.
Full backward compatibility with previous CXL specifications was also ensured by the consortium.
“We are pleased to announce the release of the CXL 3.2 specification to advance the CXL ecosystem by providing improvements to the security, compliance and functionality of CXL memory devices,” said Larrie Carr, president of the CXL Consortium.
“The Consortium continues to develop an open, coherent interconnection and enable an interoperable ecosystem for heterogeneous memory and computing solutions.”